
IR1166S
Application Information and Additional Details
State Diagram
UVLO/Sleep Mode
The IC remains in the UVLO condition until the voltage on the VCC pin exceeds the VCC turn on threshold voltage, V CC
ON . During the time the IC remains in the UVLO state, the gate drive circuit is inactive and the IC draws a quiescent
current of I CC START . The UVLO mode is accessible from any other state of operation whenever the IC supply voltage
condition of VCC < V CC UVLO occurs.
The sleep mode is initiated by pulling the EN pin below 2.5V (typ). In this mode the IC is essentially shut down and
draws a very low quiescent supply current.
Normal Mode
The IC enters in normal operating mode once the UVLO voltage has been exceeded. At this point the gate driver is
operating and the IC will draw a maximum of I CC from the supply voltage source.
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? 2013 International Rectifier
Nov 6, 2013